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si9124 vishay siliconix new product document number: 72099 s-03638?rev. b, 20-mar-03 www.vishay.com 1 500-khz push-pull dc-dc converter with integrated secondary synchronous rectification control features 12-v to 72-v input voltage range compatible with etsi 300 132-2 100 v, 100-ms transients integrated push-pull 1-a primary drivers voltage mode control voltage feedforward compensation high voltage pre-regulator operates during start-up current sensing on out b primary device hiccup current control during shorted load low input voltage detection programmable soft-start function programmable oscillator frequency over temperature protection applications network cards power supply modules description si9124 is a dedicated push-pull controller ic ideally suited to fixed telecom dc-dc converter applications where high efficiency is required at low output voltages (e.g. <3.3 v). designed to operate within the voltage range of 12-72 v and withstand 100 v, 100 ms transients, the ic is capable of controlling and directly driving both primary side mosfet switches of a push-pull circuit. high conversion efficiency is achieved by use of synchronous rectifying mosfet transistors in the secondary. due to the very low on-resistance of the secondary mosfets, a significant increase in the efficiency can be achieved as compared with conventional schottky diodes for today?s low output voltages. on-chip control of the dead time delays between the primary and secondary signals keep ef ficiencies high and prevents accidental destruction of the power transformer or wasted energy from self timed approaches. such a system can achieve conversion efficiencies well in excess of 90%. functional block diagram pulse transformer - figure 1. voltage control current control pre-reg primary drivers secondary driver error amp opto c load r load v out r s power transformer si9124 push-pull synchronous controller v in v cc ep cs2 voltage information to v cc c vin1 + cv cc cs1 1.215 v soft- start pwm c ss ss sec_sync v inext r ext out a out b driver logic
si9124 vishay siliconix new product www.vishay.com 2 document number: 72099 s-03638?rev. b, 20-mar-03 description (continued) si9124 has advanced current monitoring circuitry to permit the user to set the maximum current in the primary circuit. such a feature acts as protection against output shorts. upon sensing an overload condition, the converter is shut off for a period of time and then soft-start cycle is re-initiated, achieving hiccup mode operation. current sensing is by means of a sense resistor on the primary device. an integrated over-temperature shutdown circuit also protects the system. the 100-v depletion mode mosfet integrated pre-regulator circuit permits direct operation from input voltage with only one series resistor during startup. the pre-regulator automatically disconnects from the input supply when the output voltage is established by means of a feedback winding from the filter inductor. si9124 is available in tssop-16 pin package. in order to satisfy the stringent ambient temperature requirements, si9124 is rated to handle the industrial temperature range of ?40 to 85 c. detailed block diagram 1.65 v v ff - + pre-regulator - + - + v indet v ref v in + - 2.2 r ep - + pwm comparator ss - + cs2 cs1 over current protection gnd v uvlo v uv v sd v cc hiccup mode start driver control and timing otp osc r osc ramp sec_sync pgnd out a sec_sync driver primary b driver level shift v cc2 pgnd 2 si9124 peak det r i v ref error amplifier 4i primary a driver gain v cc v cc figure 2. 8.8 v 550 mv out b
si9124 vishay siliconix new product document number: 72099 s-03638?rev. b, 20-mar-03 www.vishay.com 3 absolute maximum ratings (all voltages referenced to gnd = 0 v) v in (continuous) 75 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v in (100 ms) 100 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v cc 14.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v cc2 14.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ref , r osc - 0.3 v to v cc + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . logic inputs - 0.3 v to v cc + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog inputs - 0.3 v to v cc + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sec_sync drive current 35 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . hv pre-regulator input current (continuous) 5 ma . . . . . . . . . . . . . . . . . . . . . storage temperature - 65 to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating junction temperature 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation a tssop-16 (t a = 25 c) 1.25 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . thermal impedance ( ja ) tssop-16 b 100 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes a. device mounted on jedec compliant 1s2p (4 layer) test board. b. derate - 10 mw/ c above 25 c. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating range (all voltages referenced to gnd = 0 v) v in 36 to 72 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c vin1 c vin2 100 f/esr 100 m and 0.1 f . . . . . . . . . . . . . . . . . . . . . . . v cc operating 10 to 13.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cv cc 4.7 f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f osc 200 to 600 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . r osc 24 to 72 k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . r ext 1.4 k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c ss 22 nf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c ref 1.0 f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c boost 0.1 f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c load 150 f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog inputs 0 to v cc - 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs 0 to v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference voltage output current 0 to 2.5 ma . . . . . . . . . . . . . . . . . . . . . . . . . specifications a test conditions unless specified cs1 = cs2 = 0 v, f nom = 500 khz, v in = 48 v limits - 40 to 85 c parameter symbol cs1 = cs2 = 0 v , f nom = 500 kh z, v in = 48 v v indet = 4.8 v; 10 v v cc 13.2 v, v cc2 = v cc min b typ c max b unit reference (3.3 v) output voltage v ref v cc = 12 v, 25 c load = 0 ma 3.2 3.3 3.4 v short circuit current i sref v ref = 0 v -50 ma load regulation dvr/dlr i ref = 0 to - 2.5 ma -30 -75 mv power supply rejection psrr @ 100hz 60 db oscillator accuracy (1% r osc ) r osc = 30 k , f nom = 500 khz -20 20 % max frequency f max r osc = 24 k 600 khz error amplifier input bias current i bias v ep = 0 v -40 -15 a gain a v - 2.2 v/v bandwidth bw 5 mhz power supply rejection psrr @ 100hz 60 db slew rate sr 0.5 v/ s current sense amplifier input v oltage cm range v cm v cs1 - gnd, v cs2 - gnd 150 mv input amplifier gain a vol 17.5 db input amplifier bandwidth bw 5 mhz input amplifier offs et voltage v os 5 v cc hiccup threshold v thcup increase cs2 until ss hiccups 150 mv hysteresis decrease cs2 until ss clamps -50 mv
si9124 vishay siliconix new product www.vishay.com 4 document number: 72099 s-03638?rev. b, 20-mar-03 specifications a limits - 40 to 85 c test conditions unless specified cs1 = cs2 = 0 v, f nom = 500 khz, v in = 48 v v indet = 4.8 v; 10 v v cc 13.2 v, v cc2 = v cc parameter unit max b typ c min b test conditions unless specified cs1 = cs2 = 0 v, f nom = 500 khz, v in = 48 v v indet = 4.8 v; 10 v v cc 13.2 v, v cc2 = v cc symbol pwm operation duty cycle e d max f osc = 500 khz v ep = 0 v 90 92 95 % d uty c yc l e e d min f osc = 5 00 kh z v ep = 1.85 v 15 % pre-regulator input voltage (continuous) v in i in = 10 a 72 v input leakage current i lkg v in = 72 v, v cc v reg 10 a regulator bias current i reg1 v in = 72 v, v indet v sd 86 200 a regulator bias current i reg2 v in = 72 v, v indet v ref 4.5 7.5 ma pre-regulator drive capacility i start v cc v reg 20 ma v pr lt t off v reg1 v indet v ref 7.4 9.1 10.4 v cc pre-regulator turn off threshold voltage v reg1 v indet v ref t a = 25 c 8.5 9.1 9.7 th res h o ld v o lt age v reg2 v indet = 0 v 9.2 v undervoltage lockout d v uvlo v cc rising 7.15 8.6 9.8 v undervoltage lockout d v uvlo v cc rising t a = 25 c 8.1 8.6 9.3 v uvlo hysteresis v uvlohys 0.5 soft-start soft - start current output i ss1 0 v ss 2 v be 12 20 28 a s o f t- s tart c urrent o utput i ss2 2 v be v ss 4.8 v 60 100 200 a soft-start completion voltage v ss_comp normal operation 7.35 8.1 8.85 v shutdown v indet shutdown fn v sd v indet rising 350 550 720 mv v indet hysteresis v indet 200 m v v indet input threshold voltages v indet - v in under voltage v uv v indet rising 3.13 3.3 3.46 v v indet hysteresis v indet 0.3 v over temperature protection activating temperature t j increasing 160 c de-activating temperature t j decreasing 130 c converter supply current (v cc ) shutdown i cc1 shutdown, v indet = 0 v 50 140 350 a switching disabled i cc2 v indet v ref 1.8 2.8 3.8 switching w/o load f i cc3 v indet v ref , f nom = 500 khz 3.0 4.4 6.8 switching with c load i cc4 v cc = 12 v, out a = out b = 3 nf, c sec_sync = 0.3 nf 15.2 ma v cc hiccup current i hcup cs2 - cs1 = 200 mv, c outa = c outb = 3 nf c sec_sync = 0.3 nf 4.3
si9124 vishay siliconix new product document number: 72099 s-03638?rev. b, 20-mar-03 www.vishay.com 5 specifications a limits - 40 to 85 c test conditions unless specified cs1 = cs2 = 0 v, f nom = 500 khz, v in = 48 v v indet = 4.8 v; 10 v v cc 13.2 v, v cc2 = v cc parameter unit max b typ c min b test conditions unless specified cs1 = cs2 = 0 v, f nom = 500 khz, v in = 48 v v indet = 4.8 v; 10 v v cc 13.2 v, v cc2 = v cc symbol output a primary driver output high v oltage v oh sourcing 10 ma v cc2 - 0.3 v output low voltage v ol sinking 10 ma pgnd 2 + 0.3 v v cc2 current i cc5 0.1 1.55 1.1 ma peak output source i source v cc2 = 12 v, pgnd 2 = 0 v - 1.0 - 0.75 a peak output sink i sink v cc2 12 v, pgnd 2 0 v 0.75 1.0 a rise time t r t a = 25 c c outa = 3 nf v cc = 12 v 20 80% 18 28 ns fall time t f t a = 25 c, c outa = 3 nf, v cc = 12 v, 20 - 80% 22 28 ns output b primary driver output high v oltage v oh sourcing 10 ma v cc - 0.3 v output low voltage v ol sinking 10 ma 0.3 v peak output source i source v cc = 12 v pgnd = 0 v - 1.0 - 0.75 a peak output sink i sink v cc = 12 v, pgnd = 0 v 0.75 1.0 a rise time t r t a = 25 c c outb = 3 nf v cc = 12 v 20 80% 19 28 ns fall time t f t a = 25 c, c outb = 3 nf, v cc = 12 v, 20 - 80% 24 28 ns secondary_synchronous driver output high v oltage v oh sourcing 10 ma v cc - 0.4 v output low voltage v ol sinking 10 ma 0.4 v leading edge delays t d1 t a = 25 c v cc = 12 v l x = 48 v see figure 3 80 110 leading edge delays t d3 t a = 25 c, v cc = 12 v, l x = 48 v, see figure 3 80 110 ns trailing edge delays t d2 c outa = c outb = 3nf c sec sync = 0 3 nf 80 110 ns trailing edge delays t d4 c outa = c outb = 3nf, c sec_sync = 0.3 nf 80 110 peak output source i source v cc = 12 v - 100 ma peak output sink i sink v cc = 12 v 100 ma rise time t r t a = 25 c c sec sync = 0 3 nf v cc = 12 v 20 80% 16 28 ns fall time t f t a = 25 c, c sec_sync = 0.3 nf, v cc = 12 v, 20 - 80% 17 28 ns voltage mode error amplifier t d1a input to a-side switch off 200 ns e rror a mp lifi er t d1a t d2b input to b-side switch off 200 ns current mode current amplifier t d3a input to a-side switch off 200 ns c urrent a mp lifi er t d3a t d4b input to b-side switch off 200 ns notes a. refer to process option flowchart for additional information. b. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum ( - 40 to 85 c). c. typical values are for design aid only, not guaranteed nor subject to production testing and are measured at v cc = 12 v unless otherwise noted. d. v uvlo tracks v reg1 by a diode drop. e. measured on out a or out b outputs. f. note total supply current drawn is i cc3 plus i cc5 .
si9124 vishay siliconix new product www.vishay.com 6 document number: 72099 s-03638?rev. b, 20-mar-03 timing diagrams for mos drivers time v cc gnd v cc sec_sync 50% 50% gnd v cc 50% 50% leading trailing leading trailing t d3 t d4 t d1 t d2 gnd figure 3. gnd gnd figure 4. soft-start, hiccup mode operation out a out b v cc sec_sync out a out b v cc volts 2 v be gnd time ss soft start hiccup time out over current detected t 1 t 2
si9124dq (tssop-16) 16 15 14 13 1 2 3 4 12 11 10 9 5 6 7 8 v in v cc2 out a v cc pgnd 2 v ref out b gnd pgnd r osc sec_sync ep ss v indet cs2 top view cs1 si9124 vishay siliconix new product document number: 72099 s-03638?rev. b, 20-mar-03 www.vishay.com 7 pin configuration ordering information part number temperature range package SI9124DQ-T1 40 to 85 c tape and reel si9124dq - 40 to 85 c bulk pin description pin number name function 1 v in input supply voltage for the start-up circuit. 2 v cc supply voltage for internal circuitry 3 v ref 3.3-v reference, decoupled with 1- f capacitor 4 gnd analog ground 5 r osc external resistor connection to oscillator 6 ep voltage control input 7 v indet v in under voltage detect and shutdown function input. shuts down or disables switching when v indet falls below preset threshold voltages and provides the feed forward voltage. 8 cs1 current limit amplifier negative input 9 cs2 current limit amplifier positive input 10 ss soft-start control - external capacitor connection 11 sec_sync secondary side timing signal 12 pgnd a driver power ground. 13 out b b gate drive signal ? primary 14 pgnd 2 b driver power ground 15 out a a gate drive signal ? primary 16 v cc2 v cc2 connect to v cc
si9124 vishay siliconix new product www.vishay.com 8 document number: 72099 s-03638?rev. b, 20-mar-03 detailed functional block diagram figure 5. + - 132 k ep + - - + - + v reg 9.1 v v cc v in pre-regulator v uvlo 8.6 v reference voltage 3.3 v voltage feedforward osc 160 c temp protection v sd v uv v uvlo logic clock otp v ref v indet - + r osc oscillator clock 60 k v ref /2 pwm generator - + - + v uv v sd v ref 550 mv logic out a v cc2 pgnd 2 primary a driver out b sec_sync pgnd primary b driver secondary synchronous driver gnd current control gain 100 mv cs2 cs1 v cc v cc blanking ss enable v cc 20 a 80 a ss control ss v ref 9.1 v detailed operation start-up a detailed functional block diagram is shown in figure 5 with additional detail of the pre-regulator shown in figure 6 . the pre-regulator circuit acts as a linear regulator to provide v cc directly from the v inext supply until the v cc supply voltage between 10 v to 13.2 v can be sustained from an auxiliary winding from the secondary of the power inductor. when v inext rises above 0 v (see figure 6), the internal pre-regulator begins charging the external capacitor on v cc . the charging current is limited to typically 40 ma by the internal dmos device. when vcc exceeds the uvlo voltage of 8.8 v, a soft-start cycle of the controller is initiated to provide power to the secondary. once switching commences, the internal gate drivers for the primary side switching transistors and the drive current into the secondary synchronization driver draw additional current from the v cc capacitor and pre-regulator.
si9124 vishay siliconix new product document number: 72099 s-03638?rev. b, 20-mar-03 www.vishay.com 9 the pre-regulator will remain on until v cc equals v reg but between v uvlo and v reg , excessive current may result in v cc falling below v uvlo and stopping soft start operation. this situation is avoided by the hysteresis between v reg and v uvlo and correct sizing of the v cc capacitor, bootstrap capacitor, the soft-start capacitor, the primary mosfet gate driving charge, and load on the sec_sync output. the value of the v cc capacitor should be chosen to be capable of maintaining soft start operation with v cc above v uvlo until the v cc current can be supplied from the external circuit (e.g. via an auxiliary winding on the secondary inductor). c vcc 4.7 f gnd v cc v ref v in v inext figure 6. high-v oltage pre-regulator circuit hv dmos 14.5 v r ext = 1.4 k auxillary v cc the feedback voltage from the output of the auxiliary winding must sustain v cc above v reg to fully disconnect the pre-regulator, isolating v cc from v inext . v cc is then maintained above v reg for the duration of operation. in the event of an over voltage condition on v cc , an internal voltage clamp turns on at 14.5 v to shunt excessive current to gnd. in systems where operation is directly from a 12 v supply, v inext and v cc can be connected to the 12 v bus. the soft-start circuit is designed for the dc-dc con verter to start up in an orderly manner and reduce component stress. soft start is achieved by ramping the maximum achievable duty cycle during the soft start time. the duty cycle is increased from zero to the final value at the rate set by the an external capacitor, c ss as shown in figure 7. the hiccup time is set by an internal 20 a current source charging c ss from 0 v to 2 v be , at which point switching begins. then a 100 a charging current is applied to c ss to charge from 2 v be to the final value controlling the duty cycle as it rises. in the event of uvlo, shutdown or over current, the ss pin will be held low ( 1 v) disabling driver switching. a longer soft-start time may be needed for highly capacitive loads and high peak-output current applications. in the event of an over current condition being detected, the soft-start pin will be pulled low and the cycle will start again performing a hiccup as shown in figure 4. the hiccup off-time, t 1 , is given by: t 1 c ss 1.2 v 20 a the soft-start time t 2 is can be estimated as: t 2 c ss v out n ( k 100 a ) where v out is the output of the converter, and n is the turns ratio of the primary to each secondary winding, and k is the ratio of the resistive divider from v inext to v indet (typically 10/1). - + gm c ss + - av a v 150 mv peak detect blank cs1 cs2 ss control figure 7. current-sense and soft-start circuit block diagram a v 100 mv i 4i v cc ss ss enable
si9124 vishay siliconix new product www.vishay.com 10 document number: 72099 s-03638?rev. b, 20-mar-03 care should be taken to control the operating time using the internal preregulator to prevent excessive power dissipation in the ic. the use of an external dropping resistor connected in series with the v in pin to drop the voltage during start up is recommended. the value of r ext is selected to drop the input voltage to the ic under worst case conditions thereby dissipating power in the resistor, instead of the ic. if the supply output is shorted and the auxiliary winding does not provide the v cc current, then continuous soft start cycles will occur. the average power in the ic during start-up where the hiccup operation would be performed continuously is given by: power ( ic ) v in t 1 i cc2 t 2 i cc4 i cc5 i sec_sync t 1 t 2 power r ext v id t 1 i cc2 t 2 i cc4 i cc5 i sec_sync t 1 t 2 where v id v inext v in where i cc2 is the non-switching supply current, i cc4 and i cc5 are the supply current while switching, and i sec_sync is the average current out of the sec_sync pin, and t 1 and t 2 are defined in figure 4 . after the feedback voltage from the secondary overrides the internal pre-regulator, no current flows through r ext . an example of the feedback circuitry is shown in figure 15. the ss pin has a predictable +1.25-mv/ c temperature coefficient and can be used to continuously monitor the junction temperature of the ic for a given power dissipation. reference the reference voltage of si9124 is set at 3.3 v. the reference voltage should be de-coupled externally with a 0.1 f capacitor. the v ref voltage is 0 v in shutdown mode and has 50-ma source capability. voltage mode pwm operation under normal load conditions, the ic operates in voltage mode and generates a fixed frequency pulse-width modulated signal to the drivers. duty cycle is controlled over a wide range to maintain the output voltage under line and load variation. voltage feed-forward is also included to improve line regulation and transient response. in the push-pull topology requiring isolation between output and input, the reference voltage and error amplifier must be supplied externally, usually on the secondary side. the error information is usually passed to the power controller through an opto-coupling device for isolation. the error information enters the ic via pin ep and where 0 v results in the maximum duty cycle, whilst 2 v represents minimum duty cycle. the ep error signal is gained up by -2.2x via an inverting amplifier and compared against the internal ramp generator. the relationship between duty cycle and v ep is shown in the t ypical characteristic section, duty cycle vs. v ep at 25 c , page 12. voltage feed-forward is implemented by taking the attenuated v inext signal at v indet to directly modulate he duty cycle. this relationship is shown in the typical characteristic section, duty cycle vs. v indet , page 12. the response time to line transients is very short since the pwm duty cycle is charged directly without having to go through the error amplifier feedback loop. at start-up, i.e., once v cc is greater than v uvlo , switching is initiated under soft-start control which increases maximum attainable switch on-time linearly over the soft-start period. start-up from a v indet power down, over-temperature, or over current is also initiated under soft-start control. push-pull and synchronous rectification timing sequence the pwm signal generated within the ic controls the out a and out b drivers on alternate cycles. a period of inactivity always results after initiation of the soft-start cycle until the soft-start voltage reaches approximately 2 v be and pwm generated switching begins. the timing and coordination of the drives to the primary and secondary stages is very important and the relationships are shown in figure 3. it is essential to avoid the situation where both of the secondary mosfets are on when either the out a or out b switches are active. in this situation the transformer would effectively be presented with a short across the output. to avoid this a timing signal is made available which is ahead of the primary drive outputs by 80 ns. primary mosfet drivers the drive voltage for the primary mosfets is provided directly from the v cc and v cc2 supply. the switch gate drive signals out a and out b are shown in figure 3. the drive currents for the primary side mosfets is supplied from the v cc and v cc2 supply and can influence start up conditions. secondary synchronization driver the secondary side mosfets are driven by the sec_sync output via a pulse transformer and gate driver circuits. the time relationships are shown in figure 3. logic circuitry on the secondary side is required to align the synchronous rectifier gate drive with the primary drive. the current supplied to the pulse transformer is drawn from v cc . oscillator the oscillator is designed to operate at a frequencies up to 500 khz. the 500-khz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. the oscillator and therefore the switching frequency is programmable by a resistor on the r osc pin. the relationship is shown in the typical characteristics, f osc vs. r osc .
si9124 vishay siliconix new product document number: 72099 s-03638?rev. b, 20-mar-03 www.vishay.com 11 hiccup operation current limiting is achieved by monitoring the differential voltage between cs1 and cs2 pins which are connected across a primary sense resistor. once the differential voltage exceeds the 150-mv trigger point, hiccup operation is started. the soft-start voltage on the ss pin is pulled to ground and switching stops until the ss pin charges up to 2 v be whereupon a duty cycle limited soft start is initiated. the upper and lower switching points of the current limit have 50 mv of hysteresis. v inext voltage monitor ? v indet the si9124 provides a means of sensing the voltage on v inext to control the operating mode and provides the feed-forward control voltage to the pwm controller. this is achieved by choosing an appropriate resistive tap between v inext and ground. when the v indet voltage is greater than 720 mv but less than v ref and v cc is greater than v uvlo , all internal circuitry is enabled, but switching is stopped. v indet also provides the input to the voltage feed-forward function by adjusting the amplitude of the pwm ramp to the pwm comparator. shutdown mode if v indet pin is forced below 470 mv the device will enter shutdown mode. this powers down all unnecessary functions of the controller, ensures that the primary switches are off and results in a low level current demand of 150 a from the v inext or v cc supplies. typical characteristics 7.5 8.0 8.5 9.0 9.5 10.0 - 50 - 25 0 25 50 75 100 125 150 7.90 7.95 8.00 8.05 8.10 8.15 8.20 - 50 - 25 0 25 50 75 100 125 150 v reg vs. temperature, v in = 48 v temperature ( c) (v) v reg v indet v ref t c = - 11 mv/c v ss vs. temperature, v cc = 12 v temperature ( c) (v) v ss t c = +1.25 mv/c v indet v ref 15 17 19 21 23 25 - 50 - 25 0 25 50 75 100 125 i ss1 vs. v cc vs. t emperature temperature ( c) v cc = 13 v 80 90 100 110 120 130 140 - 50 - 25 0 25 50 75 100 125 i ss2 vs. v cc vs. t emperature tem p erature ( c ) v cc = 10 v v cc = 12 v v cc = 13 v v cc = 10 v v cc = 12 v (ua) i ss1 (ua) i ss1
si9124 vishay siliconix new product www.vishay.com 12 document number: 72099 s-03638?rev. b, 20-mar-03 typical characteristics 0 10 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 out a , out b duty cycle vs. v ep v ep (v) 40 60 80 100 120 - 50 - 25 0 25 50 75 100 125 out a , out b delay vs. t emperture duty cycle (%) temperature ( c) delay (ns) v cc = 12 v t d1 , t d3 t d2 , t d4 3.6 v = v indet v cc = 12 v 7.2 v 4.8 v 30 40 50 60 70 80 90 100 2.5 3.5 4.5 5.5 6.5 7.5 v indet (v) duty cycle % out a , out b duty cycle vs. v indet @ 25 c v ep = 1.2 v, v cc = 9.5 v i hcup vs. ss duty cycle, c ss 22 = nf ss duty cycle (%) = t 2 / (t 1 + t 2 ) i hcup (ma) 3.270 3.275 3.280 3.285 3.290 3.295 3.300 - 50 - 25 0 25 50 75 100 v ref vs. temperature, v cc = 12 v temperature ( c) (v) v ref 200 300 400 500 600 20 30 40 50 60 70 80 f osc vs. r osc @ v cc = 12 v r osc (k ) (khz) f osc 6 7 8 9 10 11 12 13 14 10 20 30 40 50 v cc = 12 v v iindet = 4.8 v out a = out b = 3 nf c sec_sync = 0.3 nf
si9124 vishay siliconix new product document number: 72099 s-03638?rev. b, 20-mar-03 www.vishay.com 13 typical characteristics 0 50 100 150 200 250 0 200 400 600 800 v cc = 12 v 0 5 10 15 20 25 30 35 0 200 400 600 800 0 5 10 15 20 25 30 35 0 200 400 600 800 out a , out b i sink vs. v ol i sink (ma) v ol (mv) v ol (mv) sec_sync i source vs. v oh sec_sync i sink vs. v ol v oh (mv) i sink (ma) i source (ma) v cc = 12 v v cc = 12 v 0 50 100 150 200 250 0 200 400 600 800 out a , out b i source vs. v oh v oh (mv) i source (ma) v cc = 12 v 4.0 4.5 5.0 5.5 6.0 - 50 0 50 100 temperature ( c) drivers w/o c load v cc = 12 v i cc5 + i cc3 (ma) i cc3 + i cc5 vs. t emperature 3.5 4.0 4.5 5.0 5.5 - 50 0 50 100 i reg2 vs. t emperature i reg2 (ma) temperature ( c) drivers w/o c load v in = 48 v
si9124 vishay siliconix new product www.vishay.com 14 document number: 72099 s-03638?rev. b, 20-mar-03 typical waveforms 200 s/div figure 8. over current hiccup (cs2 = 200 mv) figure 9. over current hiccup cycle figure 10. pre-regulator start-up figure 11. operating driver waveforms figure 12. sec_sync set-up time (t d3 , t d4 ) figure 13. sec_sync set-up time (t d1 , t d2 ) cs2 100 mv/div 10 v/div out a 5 v/div sec_sync 5 v/div 2 ms/div 100 ns/div 500 ns/div 100 ns/div 200 s/div ss 1 v/div cs2 100 mv/div out b 20 v/div ss 1 v/div out a 20 v/div out b 5 v/div out a 5 v/div sec_sync 5 v/div sec_sync 5 v/div out b 5 v/div v cc = 12 v v cc = 12 v v cc = 12 v out b 20 v/div out a 20 v/div v inext v cc gnd c ss = 22 nf v cc = 12 v c ss = 22 nf v cc = 12 v
si9124 vishay siliconix new product document number: 72099 s-03638?rev. b, 20-mar-03 www.vishay.com 15 logic representative application schematic 5 v aux 5 v d3 1n4001 v aux +5 v 1 3 1 4 ta b gnd v in v out gnd c37 c36 0.1 f 0.1 f gnd r33 470 d1b bat54s d1a bat54s clx d clr pre +5 v +5 v 1 2 3 4 tx out c35 0.1 f r31 10 d1b bat54s d1a bat54s r32 1 k +5 v c36 10 f q q l2a 74hc74 5 6 2 l3a 74ac32 l3b 74ac32 5 clx d clr pre 13 12 11 10 q q l2a 74hc74 9 8 gnd +5 v +5 v d1b bat54s d1a bat54s r34 470 6 3 +5 v 1 r35 5 k r36 5 k r37 1 k v out q5 2n3904 2 3 4 1 2 l4a l4b gate a gate b u1 5 v reg 74ac00 74ac00 figure 14. out n out p
si9124 vishay siliconix new product www.vishay.com 16 document number: 72099 s-03638?rev. b, 20-mar-03 2 6 3 4 5 1 q7b q7a si3552dv c9 1 f r6 35 k c30 200 - 800 pf v ref c1 1 f 100 v r27 1.4 k v in v cc2 out a v cc pgnd2 out b gnd pgnd r osc ep v indet ss c s1 q1 si4490dy q2 si4490dy representative application schematic diagram si9124 sec_sync c s2 c29 470 pf r1 90 k r5 10 k c2 1 f 100 v c3 15 f 100 v + c4 15 f 100 v + q3 si4886dy q4 si4886dy d4 30bq040 r14 3.3 c15 1 nf push - pull t1 q5 si4886dy q6 si4886dy d5 30bq040 r15 3.3 c16 1 nf d8 das19 v in - v in + r19 2.2 k c28 1 nf - + t2 ep7 tx_out out p out n gnd v aux gate a logic gate b c25 33 nf c27 0.1 f c19 4.7 f 16 v + vin ext gnd 8:2:2 + 2:1 1 2 u2 moc207 7 6 5 2 6 3 4 5 1 q8b q8a si3552dv r22 33 k r23 18.6 k r16 10 c33 0.1 f + u4 lm4041c1m3 - 1.2 c26 0.1 f r25 2 k u3 lm7301 r18 300 k r26 5.6 k out_gnd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 1, 2, 3 1, 2, 3 5, 6, 7, 8 4 4 4 1, 2, 3 5, 6, 7, 8 5, 6, 7, 8 4 1, 2, 3 4 1, 2, 3 5, 6, 7, 8 4 1, 2, 3 5, 6, 7, 8 6 7 3 2 4 1 2 3 d11 smaj12ca 5, 6 7, 8 3,4 9, 10 1, 2 5, 6, 7, 8 c10 4.7 f 16 v r7 c11 1 nf 2 k r11 2 k c12 15 pf 2 k r12 0.01 10 9 r10 c14 22 nf + + c22 47 f 10 v c23 47 f 10 v t3 lep-9080 1:3 c24 47 f 10 v c32 10 f 6.3 v vout d7 30bq040 d6 mbr0520 + + 1, 2, 3 5 4 7, 8, 9 3.3 v r24 1 m c34 0.1 f c21 0.047 f out_gnd 11, 12 v out figure 15. 5 v

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